1. Field of the Invention
The present invention relates to a method of forming a multilayered wiring structure of a semiconductor device.
2. Description of the Related Art
A multilayered wiring structure in a large scale integrated semiconductor circuit (LSI) is frequently used to give a wide margin of coupling elements arranged in a semiconductor substrate and form a high-density, high-speed device.
FIGS. 1A to 1H are sectional views for explaining the steps in forming a multilayered wiring structure of a conventional semiconductor device. As shown in FIG. 1A, in formation of a conventional multilayered wiring structure, an insulating layer 2 is formed on the surface of a semiconductor substrate 2 and is selectively removed so as to allow connections with the substrate 1. An aluminum film is deposited on the entire surface of the resultant structure and is patterned to form at least two lower wiring layers 3a and 3b adjacent to each other. Each lower wiring layer is formed in advance to have a dimension corresponding to a diameter of a via hole. In order to form upper wiring layers, an insulating interlayer 4 is formed on the insulating film 2 and the first and second lower wiring layers 3a and 3b, and the insulating interlayer 4 is planarized by a known resist etch-back method. As shown in FIG. 1B, a resist 5 is formed on the insulating interlayer 4 and is patterned into a predetermined pattern in accordance with a known photolithographic technique. The resist 5 must be patterned to have openings corresponding to the sizes of the via holes. As shown in FIG. 1C, openings 6a and 6b for contact holes are formed in parts of the insulating interlayer 4 on the first and second lower wiring layers 3a and 3b using the resist 5 having the predetermined pattern as a mask in accordance with a known reactive ion etching technique (to be referred to as RIE hereinafter). The openings 6a and b must be formed to correspond to the lower wiring layers 3a and 3b, respectively. As shown in FIG. 1D, the resist 5 is removed. As shown in FIG. 1E, an aluminum film 7 for the upper wiring layers is formed on the insulating interlayer 4 including the lower wiring layers 3a and 3b in the openings. As shown in FIG. 1F, a resist 5 is formed on the aluminum layer 7 and is patterned to have a predetermined pattern in accordance with the known photolithographic technique. As shown in FIG. 1G, the aluminum film 7 on the insulating interlayer 4 between the lower wiring layers 3a and 3b is partially removed using the resist 5 having the predetermined pattern in accordance with RIE, thereby forming upper wiring layers 7a and 7b which are separated from each other and electrically connected to the lower wiring layers 3a and 3b. It is noted that the aluminum film 7 is cut on the narrow portion of the insulating interlayer 4 between the lower wiring layers 3a and 3b. As shown in FIG. 1H, the resist 5 is removed by a known resist removal method. Similarly, insulating interlayers and wiring layers are alternately formed in accordance with the required number of layers, thereby realizing a multilayered wiring structure.
According to this formation method, however, the resist 5 formed on the insulating interlayer 4 between the lower wiring layers 3a and 3b has a very narrow pattern, as shown in FIG. 1C. For example, assume that the distance between the two lower wiring layers is 1.2 .mu.m, and that openings each having a taper angle of 75.degree. with respect to a 1-.mu.m thick insulating interlayer are formed. In consideration of a dimensional conversion error of 0.1 .mu.m, the resist 5 formed on the insulating interlayer 4 between the lower wiring layers 3a and 3b has a very narrow pattern with a width of 0.57 .mu.m or less. For this reason, when the openings are to be formed, if the resist floats or is peeled, openings 6a and 6b having stable shapes cannot be obtained. For this reason, upper wiring layers 7a and 7b cannot be stably patterned. As a result, short-circuiting occurs between the upper wiring layers, and disconnections occur in the upper wiring layers. In resist patterning, if a mask alignment error occurs, a groove 8 is undesirably formed in the side wall of the lower wiring layer by overetching in formation of the openings, as shown in FIG. 1C. In deposition of the aluminum film for the upper wiring layers, since the width of the groove 8 is very narrow, the groove 8 cannot be covered with the Al film. As a result, as shown in FIG. 1H, a void 9 is formed to decrease the product yield and degrade reliability.
FIGS. 2A to 2H are sectional views for explaining the steps of forming a multilayered wiring stricture of another conventional semiconductor device. In this example, one lower wiring portion 303 and the other wiring portion 304 have different levels. As shown in FIG. 2A, a first insulating film 302 is formed on the surface of a semiconductor substrate 301 having a polycrystalline semiconductor layer 313 or the like. After necessary portions of the first insulating film 302 which are required for connections with the substrate 301 are removed, an aluminum film is deposited on the entire surface of the resultant structure and is patterned, thereby forming the first wiring portion 303 having at least two lower wiring layers 303a and 303b adjacent and electrically connected to each other on the lower portion of the first insulating film 302, and also forming the second wiring portion 304 having at least two lower wiring layers 304a and 304b adjacent and electrically connected to each other on the upper portion of the first insulating film 302. To form upper wiring layers, an insulating interlayer 305 is formed on the first insulating film 302 and the lower wiring layers 303a, 303b, 304a, and 304b of the wiring portions 303 and 304 and is planarized in accordance with the known etch-back method. As shown in FIG. 2B, a resist 306 is formed on the insulating interlayer 305 and is patterned into a predetermined pattern in accordance with the known photolithographic technique. As shown in FIG. 2C, openings 307a, 307b, 308a, and 308b for contact holes are formed in parts of the insulating interlayer 305 on the lower wiring layers 303a, 303b, 304a, and 304b using the resist 306 having the predetermined pattern as a mask in accordance with known tapered reactive ion etching (to be referred to as tapered RIE hereinafter). The openings are formed to correspond to the lower wiring layers 303a, 303b, 304a, and 304b, respectively. As shown in FIG. 2D, the resist 306 is removed by the known resist removal method. As shown in FIG. 2E, an aluminum film 309 for upper wiring layers is formed on the insulating interlayer 305 so as to include the lower wiring layers 303a, 303b, 304a, and 304b in the openings. As shown in FIG. 2F, a resist 306 is formed on the aluminum film 309 and is patterned into a predetermined pattern in accordance with the known photolithographic technique. As shown in FIG. 2G, the aluminum film 309 is partially removed from the insulating interlayer 305 present between the lower wiring layers 303a and 303b and between the lower wiring layers 304a and 304b using the resist 306 having the predetermined pattern as a mask, thereby obtaining independent upper wiring layers connected to the lower wiring layers 303a, 303b, 304a, and 304b. Thereafter, as shown in FIG. 2H, the resist 306 is removed by the known resist removal method. Insulating interlayers and wiring layers are alternately formed, as needed, to obtain a multilayered wiring structure.
However, again, according to this formation method, since the distance between the lower wiring layers is reduced, the resist 306 formed on the insulating interlayer 305 between the lower wiring layers 303a and 303b and between the lower wiring layers 304a and 304b inevitably has a very narrow pattern, as shown in FIG. 2C. In formation of the openings, the resist undesirably floats or is peeled. As a result, the openings 307a, 307b, 308a, and 308b cannot have a stable shape. In addition, when a mask alignment error occurs in patterning the resist, a groove 310 is formed on the side wall of the lower wiring layer by overetching in formation of the openings, as shown in FIG. 2C. For this reason, even if the aluminum film 309 serving as prospective upper wiring layers is deposited, the aluminum film 309 cannot perfectly cover the underlying structure because the groove width is very small. As a result, as shown in FIG. 2E, a cavity 311 is formed to reduce the product yield and degrade reliability.
FIGS. 3A to 3G are sectional views for explaining the steps in forming a multilayered wiring structure of still another conventional semiconductor device. In this conventional example, one lower wiring layer and the other lower wiring layer have a step. As will be described in detail below, large openings 407 and 408 are formed. This formation method is proposed by the present inventor. According to this method, a thin resist pattern need not be formed, openings each having a predetermined shape can be obtained, and formation of a groove by overetching in mask misalignment and formation of a cavity during forming the upper wiring layers can be eliminated.
As shown in FIG. 3A, a polycrystalline semiconductor layer 413, a first insulating film 402, lower wiring layers 403a and 403b constituting a first wiring portion 403, lower wiring layers 404a and 404b constituting a second wiring portion 404, and an insulating interlayer 405 are formed on a semiconductor substrate 401. As shown in FIG. 3B, after a resist 406 is formed on the insulating interlayer 405, the resist 406 is formed into a predetermined pattern in accordance with the known photolithographic technique. Openings 406a and 406b of the resist 406 are formed to have sizes including the first and second wiring portions 403 and 404, respectively. As shown in FIG. 3C, the insulating interlayer 405 exposed from the openings 406a and 406b of the resist 406 is uniformly etched to reach the first wiring portion 403 located at the lower portion in accordance with known tapered reactive ion etching (to be referred to as tapered RIE hereinafter) using the resist 406 having the predetermined pattern as a mask, thereby forming openings 407 and 408 for contact holes. At this time, a surface formed by the lower wiring layers 403a and 403b exposed in the opening 407 corresponding to the first wiring portion 403, and by an insulating interlayer portion 407a between the lower wiring layers 403a and 403b is almost flat. A surface formed by the lower wiring layers 404a and 404b exposed in the opening 408 corresponding to the second wiring portion 404, and by an insulating interlayer portion 408a between the lower wiring layers 404a and 404b has a structure with a stepped portion 410 because the etching depth is uniform. The stepped portion 410 in the second wiring portion 404 is caused by a polycrystalline semiconductor layer 413 located below the first insulating film 402 under the second wiring portion 404. For example, assume that this polycrystalline semiconductor layer 413 has a thickness of 0.4 .mu.m, and that the insulating interlayer at the insulating interlayer portion 407a between the lower wiring layers of the first wiring portion 403 has a thickness of 1.0 .mu.m. At this time, the insulating interlayer at the insulating interlayer portion 408a between the lower wiring layers of the second wiring portion 404 is 0.6 .mu.m. After the resist 406 is removed by the known resist removal method, as shown in FIG. 3D, an aluminum film 409 for upper wiring layers is formed on the first and second wiring portions 403 and 404 in the openings 407 and 408. At this time, since the stepped portion 410 forms a groove, the aluminum film 409 is deposited in a large amount and the thickness of the aluminum film is increased in this portion. As shown in FIG. 3E, a resist 406 having a predetermined pattern is formed such that openings are located above the insulating interlayer portion 407a between the lower wiring layers 403a and 403b of the first wiring portion 403 and above the insulating interlayer portion 408a between the lower wiring layers 404a and 404b of the second wiring portion 404 in accordance with the known photolithographic technique. As shown in FIG. 3F, the aluminum film 409 is partially removed on the insulating interlayer portions 407a and 408a of the first and second wiring portions 403 and 404 in accordance with RIE using the resist 406 having a predetermined pattern as a mask, thereby forming independent upper wiring layers connected to the corresponding lower wiring layers. Thereafter, as shown in FIG. 3G, the resist 406 is removed by the known resist removal method.
According to this formation method, however, as shown in FIG. 3C, when the aluminum film 409 for the upper wiring layers is deposited, the thickness of the aluminum film 409 at the stepped portion 410 is increased due to the presence of the stepped portion 410 in the second wiring portion. When the aluminum film 409 between the connecting portions is removed for insulation, an aluminum film residual portion 411 is formed between the lower wiring layers 404a and 404b, as shown in FIG. 3F. For this reason, electric insulation cannot be achieved, and failures such as short-circuiting occur. As a result, the product yield is reduced, and reliability is degraded.